In recent years progress has been made in improving the performance of and increasing the storage capacity of semiconductor memories, and chip size has increased as well. This has been accompanied by an increase in data bus length within the chip and there is a tendency toward an increase in load for driving the data bus. Further, an increase in wiring capacitance and wiring resistance of the data bus results in a larger IR-drop, and delay increases as well. Consequently, unless some measures are taken with regard to the data bus, high-speed operation may be hindered owing to power supply noise ascribable to a drop in power supply voltage or the like.
A technique for reducing the influence of a data bus on a power supply is disclosed in Patent Document 1. Specifically, an input/output device described in Patent Document 1 is provided with a function for dividing an internal data line and an internal output circuit into n types of groups and deciding from m bits of data whether to inverter or not invert all internal data within each group. As a result, power supply noise ascribable to parasitic inductance of the power supply line when the output circuit is driven can be reduced and the data transfer rate raised.
Patent Document 2 discloses a semiconductor storage device in which, by inserting relay buffers in a data bus, data transfer can be speeded up without enlarging wiring width or wiring pitch of the data bus, and in which activation/deactivation of the relay buffer circuit is controlled by using, as is, a block selection signal for block activation. In accordance with such a semiconductor storage device, efficient buffer drive control is possible in relation to chip area and operating current.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-A-09-251336[Patent Document 2]    Japanese Patent Kokai Publication No. JP-P2004-79077A